Semiconductor devices typically comprise a substrate and elements such as transistors formed from doped regions within the substrate. Interconnect layers are formed overlying the semiconductor substrate to electrically interconnect the devices and to provide a connection pad for connection to external circuit elements.
The interconnect layers are formed by employing conventional photolithographic techniques, wherein a pattern is designed on a photomask and transferred to the semiconductor chip via exposure and etching processes. A relatively thin layer of photoresist material is deposited on the substrate and exposed to a controlled pattern of radiation, causing a chemical reaction in the exposed regions. Visible light, ultraviolet radiation, electron beam or x-ray energy can be used as the developing energy depending upon the selected photoresist material. A developer solution contacts the photoresist layer to dissolve and remove either the radiation exposed areas or the radiation masked areas, depending upon the chemistry of the selected photoresist material. If the exposed areas of the photoresist layer become less soluble after exposure, the pattern remaining on the substrate is a negative image of the radiation pattern and the photoresist is referred to as a negative photoresist. If the exposed area becomes more soluble and is removed by the developer solution, the pattern remaining on the substrate is a positive image of the pattern of radiation and the photoresist is referred to as a positive-acting photoresist. In either case, when the photoresist is removed a desired region of the underlying substrate is uncovered for exposure to subsequent processing steps. The region of the substrate where the photoresist mask remains in place is protected from the subsequent processing steps. Subsequent processing steps include implanting dopants, depositing materials and applying an etchants to the surface to remove the exposed material.
Continuing advancements in semiconductor technology have promoted the fabrication of smaller devices operating at higher speeds. The drive towards such ultra large-scale integration has resulted in continued shrinking of device sizes, circuit dimensions and device features, resulting in the use of smaller masks during the photolithographic process. However, when transferring the mask pattern to the substrate, the critical dimensions of the pattern are restricted to the resolution limit of the optical exposure tool that exposes the pattern. For example, for integrated circuits comprising field-effect transistors, an important process step is the formation of the transistor gate, with particular emphasis on the dimensions of the gate. In many applications, the performance characteristics (e.g., switching speed) and the size of the transistor are functionally related to the transistor channel length, which corresponds approximately to the width of the transistor gate. Shorter channel lengths tend to produce higher performance transistors (within certain limits).
Gate line width control is thus of paramount importance in semiconductor manufacturing. As semiconductor operational speeds increase and dimensions decrease, certain techniques have been developed for forming aggressively small gate line width targets in advanced fabrication technologies. One known technique photolithographically defines the gate structure with a size somewhat larger than the final target. The gate-defining photoresist material is over-sized during the conventional photolithographic masking and patterning processes. In a subsequent etching step the photoresist is reduced in both the length and the width dimensions by exposure to an oxygen radical. Subsequent etching of the underlying conductive layer to form the gate results in a narrower gate length and width than defined by the mask dimensions.
As illustrated in FIG. 1, a conductive layer 10, comprising for example polysilicon or a conductive metal, is formed on a semiconductor substrate 12. An anti-reflective coating layer 14 overlies the conductive layer 10. Photoresist patterns 16 are formed by conventional photolithographic techniques as described above. The height (h), width (w) and spacing (s) of the photoresist patterns 16 are illustrated in FIG. 1.
In a conventional plasma etching chamber the substrate is subjected to an oxygen gas containing oxygen radicals that thin the photoresist patterns, with the resulting photoresist profile illustrated in FIG. 2, where h′ is less than h, w′ is less than w and s′ is less than s. Typically, the process is carried out at atmospheric pressure and at a relatively low temperature of between about 130° C. and 200° C. The photoresist material comprises a basic C—H—O structure that may be easily disconnected through reaction with the oxygen radical, forming CO2, CO and H2O, which are then exhausted from the process chamber.
One disadvantage of this prior art trim process is the inability to determine a process end point such that the plasma etch of the photoresist can be terminated when the end point is reached. Unlike most conventional semiconductor etch processes, the trim process does not end or terminate on an etch stop layer. When applied to the process of gate etch, the lack of a definitive end point leads to variations in the gate dimensions that can affect several performance parameters, including device speed and current leakage. The variations in the trim process can also reduce throughput, yield, and profitability if one or more of the gate dimensions are reduced beyond predetermined limits.
In an effort to overcome these disadvantages, certain statistical process control or wafer-run monitoring (“run-to-run” control) techniques have been applied to the trim tool. In either case, external metrology tools, such as a critical dimension scanning electron microscope or a scatterometer, are employed to measure the gate dimensions and control the etch trim process based on the measurement results. These measurements can be performed in situ on the fabricated gate or ex situ on the photoresist layer. However, this process control technique benefits only subsequently fabricated transistors. No real-time feedback control is provided, possibly resulting in the fabrication of defective wafers during the period between determining that a critical dimension problem exists and adjusting the process variables to overcome the problem. Further, the process adjustments are applied iteratively in an effort to alleviate the problem, as the root cause is frequently not known. Without a root cause determination, the variable adjustments may offer only a temporary fix or may not produce an immediate fix as the process is iterated toward the correct parameters. Additionally, as the chamber conditions change over time, the initial process adjustments will likely no longer be adequate.
Various process control techniques are conventionally employed to determine whether a semiconductor fabrication process tool is functioning properly. Statistical process control techniques can be utilized to identify long term statistical variations in one or more specific critical dimensions of a device. A critical dimension of interest is measured on several devices or fields within a wafer on a predetermined schedule. Based on several wafer lots, a statistical function, such as an average or a standard deviation of the measured critical dimension is calculated. As processing continues, additional fields are randomly selected from processed devices, the critical dimensions measured, and the running average or standard deviation recalculated using the latest critical dimension measurement. If the last acquired measurement does not change the average or standard deviation by more than a predetermined amount, then the process is deemed to be repeatable and no process modifications are required. If the last measurement causes the average or standard deviation to change by more than the predetermined amount then a change to the process “recipe” is warranted. Recipe changes include modifying any of the variables associated with the process tool that is causing the out-of-range feature. For example, gas pressure and/or temperature can be raised or lowered, the quantity of inlet gas per unit time can be increased or decreased, and various voltage settings can be modified in an effort to return the feature size to pre-established limits. Although this method can be used to provide a statistical analysis of a critical dimension, it cannot identify the root cause of critical dimension variations.
Run-to-run control of feature dimensions also requires the use of external metrology tools. After processing each cassette of wafers (typically 25 wafers) a plurality of critical dimensions are measured. If found to be out-of-specification, the process variables are examined in an effort to determine the cause of the anomaly and the process recipe modified in response thereto.
Although the statistical process control and run-to-run control techniques provide some feature size information for controlling a fabrication process, such as the trim rate process described above, they may not provide the desired repeatability for critical dimension control. Nor do they provide real time control over the etch rate, as the critical measurements are performed off-line and modifications are made only after confirming an out-of-specification condition.
It has been determined that the lateral etch rate for the above-described resist trim process depends on such parameters as the photolithographic pattern density, the wafer mix previously processed through the etching chamber and the cleanliness state of the chamber, i.e., the number of wafers that have been etched since the last chamber cleaning. It is believed that these factors, and likely others, influence the concentration of the available etching oxidant, in turn altering the rate at which the trim etch proceeds. According to the prior art techniques, if the statistical process control methods or run-to-run measurements indicate that the trim results are not within the predetermined bounds the flow of oxidizing gas is varied to attempt a process correction.
Certain techniques are known for controlling the trim process and attempting to reduce process variations. For example, process-specific (or tool or chamber-specific) and product-specific recipes can be devised. Thus when fabricating a certain product, the product-specific recipe for that product is employed in an effort to limit variations in the trim rate and produce a more consistent result. Similarly, when trim etching a product in a specific tool or chamber, the only the unique recipe associated with that chamber is employed. Given their different process histories and inherent physical differences, two chambers rarely employ the same recipe to fabricate the same product. Recipes can also be developed for wafers having specific photolithographic pattern densities. Observed long-term drift of the trim results, as determined by statistical process control techniques described above, can be mitigated by adjustment of the oxidant flow for all chamber-based and product-based recipes.
Whenever a new product is introduced into the manufacturing process it is preferable to monitor the trim etch results until a statistical database is created or until the effects of the trim process variables on the product is obtained. It is also important to verify the trim rate after each major etch tool hardware perturbation, such as when the chamber is cleaned.
As can be inferred from the foregoing discussion, given the significant number of variables affecting it, the trim process is cumbersome, not repeatable, and not easily controlled. Under certain worst-case conditions the process may not be usable in a manufacturing environment.